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[Embeded-SCM Develop] M430SP

Description: M430SP完整I2C代码MSP430控制LED代码及原理图PROTEL格式凌阳61A数字电子钟代码凌阳SD卡存储扩展代码凌阳数-M430SP complete control of I2C LED code and code MSP430 schematic PROTEL format 61A of digital electronic clock Sunplus Sunplus code SD memory expansion card code number Sunplus
Platform: | Size: 9441280 | Author: 王鹏 | Hits:

[SCM] 89s52clock

Description: C51编写的基于单片机的秒表时钟设计。包括原程序及原理图和PCB设计。-C51 prepared by the stopwatch clock based on single chip design. Including the original program and the schematic and PCB design.
Platform: | Size: 296960 | Author: 王明 | Hits:

[VHDL-FPGA-Verilog] Jshuqi

Description: 基于VHDL原理图实现的计数器 时钟晶振为48MHZ -Schematic-based VHDL implementation of the counter clock oscillator is 48MHZ
Platform: | Size: 196608 | Author: 张帝 | Hits:

[SCM] dianzizhong

Description: 上课时在老师指导下做的电子钟 经过反复修改 适合初学者使用学习参考 内有程序和电路图全套-Class under the guidance of the teachers do modify the clock after repeated reference for beginners to learn within the full set of procedures and schematic
Platform: | Size: 18432 | Author: yulubingde | Hits:

[SCM] temp_control

Description: 基于STC89C516RD的多功能温度,电压监测控制模块. 具有DS18B20温度检测,0~5V电压检测,实时时钟,继电器输出,步进电机控制. 通过12864(无字库)和按键进入菜单修改 管理员密码,时间设定,日期设定,闹钟设定,高低温度报警,步进电机正反转,精确步数控制. 以及该工程的电路图,PCB板图(PADS环境).-STC89C516RD based multi-function temperature and voltage monitoring and control module. Has DS18B20 temperature detection, 0 ~ 5V voltage detection, real-time clock, relay outputs, stepper motor control. By 12864 (no font) and change the administrator password to access the menu button , time set, date set, alarm settings, high and low temperature alarm, reversing the stepper motor, precise control steps. and the engineering schematic, PCB board map (PADS environment).
Platform: | Size: 814080 | Author: xuwenqiang | Hits:

[SCM] shuzhizhong

Description: 数字钟代码，包括原理图和单片机程序代码。原理图为proteus软件仿真的图片-Digital clock code, including schematic and microcontroller code
Platform: | Size: 1024 | Author: gan | Hits:

[SCM] ourdev_606645PNM2Y1

Description: 伟纳杯一等奖作品（全部原理图+PCB)红外遥控温度时钟，带上位机.-Wei satisfied Cup first prize works (all schematic+ PCB) infrared remote control temperature clock, take-bit machine.
Platform: | Size: 180224 | Author: tjiely | Hits:

[SCM] q

Description: 自己课程设计做的单片机89C52的c语言程序，主要功能为数字时钟，可设置时间，星期数。用Keil把c代码加入new project中就可以调试了。包里还有个Proteus的电路图，没上传原文件，我觉得电路图还是自己动手画画比较好吧。-My own curriculum SCM 89C52 c language program, the main function for the digital clock, can set the time, days of the week. Keil c code to use the new project in the can debug. There are a Proteus schematic bag, did not upload the original file, I think the schematic drawing is good for you.
Platform: | Size: 64512 | Author: Wang Tian | Hits:

[Embeded-SCM Develop] wannianli

Description: 彩屏显示的指针式万年历时钟，全套文件说明及原理图都在包包里面，自己慢慢看，文件好大的，有30多个M-Analog color display calendar clock, a full set of file description and schematic diagram are in the bag inside, see yourself slowly, the file very big, more than 30 M
Platform: | Size: 11671552 | Author: 孟飞 | Hits:

[VHDL-FPGA-Verilog] sy6

Description: 数字钟的VHDL源程序，里面附有数字钟的VHDL源程序和原理图的数字钟电路，数字钟有en,clk,clr等接口。-Digital clock in the VHDL source code, which the VHDL source code with a digital clock and schematic of the digital clock circuit digital clock with en, clk, clr and other interfaces.
Platform: | Size: 603136 | Author: 下世 | Hits:

[SCM] pov

Description: pov 时钟/旋转led时钟 含原理图 程序-pov clock/clock with rotating led schematic program
Platform: | Size: 46080 | Author: lgl | Hits:

[SCM] ga123

Description: HOTEK HT48R30 MCU 做的一个时钟 包括原理图 程序 与液晶图-HOTEK HT48R30 MCU to do a clock, including schematic process diagram with LCD
Platform: | Size: 173056 | Author: yuanjm | Hits:

[VHDL-FPGA-Verilog] clk_sync

Description: 本文件是在ALTERA公司的QUARTUS下VHDL+原理图编写的时钟同步逻辑-This document is in the company' s QUARTUS ALTERA under VHDL+ schematic written clock synchronization logic
Platform: | Size: 245760 | Author: 宗爱青 | Hits:

[VHDL-FPGA-Verilog] www

Description: 完整的基于fpga的数字时钟的设计与实现，压缩文档是整个文档，其中的zzz，zzz1，zzz2，zzz3不同情况下的顶层原理图-Complete digital clock fpga based design and implementation, the archive of the entire document, which zzz, zzz1, zzz2, zzz3 different top-level schematic case
Platform: | Size: 148480 | Author: 庄伟 | Hits:

[SCM] ourdev_606647DZ13Q0

Description: 伟纳杯电子设计大赛液晶12864显示电子时钟原理图-Wei Na Cup Electronic Design Contest LCD display digital clock schematic 12864
Platform: | Size: 107520 | Author: 林起锵 | Hits:

[VHDL-FPGA-Verilog] time

Description: 数字钟源代码程序，内有ahdl语言和原理图程序，已经仿真。-Digital clock source code, there ahdl language and schematic procedures have been simulation.
Platform: | Size: 188416 | Author: 小白 | Hits:

[SCM] DS1302shizhong

Description: 可调的时钟设计 有详细的说明 原理图 代码 都是整理好的-Adjustable clock design is described in detail schematic code is tidied
Platform: | Size: 105472 | Author: 高鹏 | Hits:

[SCM] DS1302

Description: 可显示时钟proteus.keil仿真详细的原理图lcd显示-Simulation can show the clock proteus.keil detailed schematic lcd display
Platform: | Size: 131072 | Author: 清清子墨 | Hits:

[VHDL-FPGA-Verilog] assignmentP2

Description: 1. Access the relevant reference books or technical data books and give accurate definitions for the following timing parameters: (1) propagation time tPD, (2) transition time tTD, (3) setup time tSU, (4) hold time tHD, and (5) clock-to-output time tCO. 2. Compare the main features of 74-393 and 74-163 counters and construct an N-bit synchronous counter using 74-163(s). 3. Macrocells (MCs) are key components of Programmable Logic Device (PLD). Based on the MC logic schematic diagram below, please describe its functions.
Platform: | Size: 172032 | Author: 魏攸 | Hits:

[VHDL-FPGA-Verilog] sy6

Description: 数字时钟，整点报时，有校分校时功能，底层用VHDL，顶层原理图-Digital clock, the whole point of time, when a school campus functions, the bottom with VHDL, top-level schematic
Platform: | Size: 4096 | Author: 1111 | Hits:
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